It has heretofore been known to use trench isolation to improve the oxide isolation scalability in bipolar processes. For example, reference is made to the article entitled, "U-Groove Isolation Technology for High Density Bipolar LSI's", Jap. J. Appl. Phys., 21, Suppl. 21-1, pp. 37-40, 1981, by Y. Tamaki, et al. In addition, trench isolation has been used in the manufacture of MOS devices, as described in such articles as "Trench Isolation Technology for MOS Applications", Proc of the First International Symposium on VLSI Science and Technology, pp. 339-346, 1982, by S. Y. Chiang, et al. Further, trench isolation has been advantageously used to suppress latch-up in bulk CMOS devices, as reported in such articles as "Deep Trench Isolated CMOS Devices", IEDM Tech. Dig., pp. 237-240, 1982, by R. D. Rung, et al.
Isolation trenches have conventionally been fabricated by the etching of deep, narrow trenches located to separate such areas as PMOS and NMOS regions. The sidewalls of previously developed trenches have then been oxidized to provide dielectric isolation and the trench refilled with a conformal undoped polysilicon deposition, which is planarized to leave polysilicon only inside the trench. Finally, a field oxide is grown on top of the trench and field regions to cap the polysilicon and to provide transistor-to-transistor isolation.
While previously developed trench isolation processes have provided improvements in oxide isolation scalability and in the suppression of latch-up, problems have occurred due to dislocations formed in the semiconductor body during the fabrication of the trench. These defects or dislocation of the semiconductor material allow high leakage current detrimental to semiconductor devices. A need has thus arisen for a trench structure and a method of fabrication which eliminates the formation of defects in the surrounding semiconductor body.